1. Field of the Invention
The present invention relates to adjustable resistors and to the use of such resistors to hide a code in an integrated circuit.
2. Discussion of Current Technologies
In certain integrated circuit technologies, especially in technologies incorporating floating-gate memories, two polysilicon layer levels are used.
FIG. 1 is a cross-section view illustrating various elements currently formed in integrated circuits using such technologies.
A memory cell 3, of the type described in patent application WO-2009/087335 of the applicants, manufactured on a silicon substrate 1, comprises a first region 5 of a layer of a first polysilicon level and a second region 7 of a layer of a second polysilicon level. Region 5 forms the floating gate of the memory cell and region 7 forms its control gate. The floating gate is insulated from substrate 1 by a thin insulator layer 9. The floating gate and the control gate are separated by an insulating layer comprising a first region 11 and a second region 12. Region 11 of the insulating layer is for example formed of an oxide-nitride-oxide (ONO) stack, for example, a silicon nitride layer between two silicon oxide layers. Region 12 is for example formed of a silicon oxide layer having a smaller thickness than the stack of region 11. Memory cell 3 further comprises two spacers 13 and source and drain regions 15. Memory cell 3 is insulated from the other integrated circuit elements by insulating areas 16.
A low-voltage (LV) MOS transistor 17, manufactured on the same substrate 1, comprises a third region 19 of the layer of the second polysilicon level, insulated from substrate 1 by a thin insulator layer 21. Polysilicon region 19 forms the gate of MOS transistor 17. MOS transistor 17 further comprises two spacers 23 and source and drain regions 25. MOS transistor 17 is insulated from the other integrated circuit elements by insulating areas 26.
A resistor 27, formed above an insulating area 29 of substrate 1, comprises a fourth region 31 of the layer of the first polysilicon level and a fifth region 33 of the layer of the second polysilicon level. Polysilicon regions 31 and 33 are insulated from each other by an insulating layer 35. Insulating layer 35 is of same nature and has been formed at the same time as insulator region 11 of memory cell 3.
First and fourth regions 5 and 31 of the layer of the first polysilicon level are N-type doped, for example, with a dopant element concentration approximately ranging from 5.1018 to 5.1019 atoms/cm3.
Elements 3, 17, and 27 are covered with an insulating overall layer 37 intended to insulate them from the first interconnect metal level. Vias 38 crossing insulator layer 37 provide access to source, drain, and gate contacting areas of MOS transistor 17 and of memory cell 3, as well as to contacting areas of resistor 27 on fourth region 31 of the layer of the first polysilicon level.
Thus, the elements of FIG. 1 use a technology of deposition and etching of a layer of a first polysilicon level, of deposition and etching of a stack of insulating layers (ONO), of forming of a thin insulator layer instead of regions of said stack, followed by the deposition and etching of a layer of a second polysilicon level. In particular, to form transistors 17, regions of the layer of the first polysilicon level and of the ONO-type stack are removed by etching and a thin insulator layer is formed above the upper surface of substrate 1 in place of said stack. Further, the steps of etching of the ONO-type stack and of forming of a thin insulator layer instead of regions of said stack, on the first polysilicon level, are also used in the specific case where memory cells 3 of the type described in patent application WO-2009/087335 of the applicants are desired to be formed.
Further, resistors of the type illustrated in FIG. 1, of different values, may be used to store a code. A first solution is to manufacture resistors of different dimensions. A second solution comprises using different dopant element concentrations in polysilicon regions 31. However, the code may easily be discovered. Indeed, a modification in the resistor dimensions can easily be detected. It is also possible to retrace the dopant element concentration in polysilicon region 31 by reverse engineering.
Thus, adjustable resistors capable of being used to hide a code in an integrated circuit are needed.